Field effect transistors (FETs), and other transistors, are electronic components commonly used to build electronic devices. For example, amplifiers, memory, and processors all are made up of several to several million transistors. Thus, a transistor's performance is largely a determining factor in the success of the electronic devices built from those transistors. Improvements in the underlying transistors can reduce noise in amplifiers, improve density and thus capacity in memory, and improve processing speed in processors.
A junction field effect transistor (JFET) is one particular kind of transistor. A JFET generally includes three terminals: a source, a drain, and a gate. By properly operating these three terminals, the JFET can be used as an amplifier in one configuration or in other circuitry in other configurations. In one mode of operation, current flows from the source to the drain through a channel of the JFET, but application of a reverse bias to the gate terminal can cause pinching of the channel and a reduction in the current flow from the source to the drain. One conventional JFET structure is shown in FIG. 1.
FIG. 1 is an example cross-section view illustrating a conventional JFET structure according to the prior art. A JFET 100 may include an n-doped well 104 in a p-doped substrate 102. A n-doped region 106 may be formed inside a p-doped region 108 within the n-doped well 104. Gate terminals 122A and 122B may be coupled to the n-doped well 104 and the n-doped region 106. A source terminal 124A may be coupled to one point of the p-doped region 108, and a drain terminal 124B may be coupled to another point of the p-doped region 108. Current flows through path 114 from the source terminal 124A to the drain terminal 124B. The path 114 may be pinched by applying a reverse bias to the gate terminals 122A and 122B, which constricts the path 114 along profile 112. Thus, current through the path 114, and thus the JFET 100, may be reduced by the application of a reverse bias at the gate terminals 122A and 122B.
The conventional JFET of FIG. 1 vertically pinches the current path between the n-doped region 106 and the n-doped well 104. However, this results in a junction capacitance around the n-doped well 104 to the substrate 102, which adds a parasitic capacitance between the gate terminals 122A and 122B and the substrate 102. The parasitic capacitance can cause undesirable behavior in the JFET 100. For example, parasitic capacitance can cause undesirable characteristics at high-frequency operation, such as by creating undesirable resonances with other components of the electronic device.
Shortcomings mentioned here are only representative and are included simply to highlight that a need exists for improved electrical components, particularly for transistors used in circuitry, such as amplifiers, employed in consumer-level devices, such as mobile phones. Embodiments described herein address certain shortcomings but not necessarily each and every one described here or known in the art.